UNIV4VINU | ENGINEERING ACHIEVERS

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PART – A(10 x 2 = 20 Marks)
1. What values remain on the stack after the following sequence of instructions are executed in a stack-based processor? The values 1 to 5 are stored in locations 1 to 50.
PUSH 23
PUSH 43
ADDPOP 35
MUL 45
POP 28
PUSH 35
PUSH 39
ADD
2. Where are the auto-increment and auto-decrement instructions useful?
3. For each of the following IEEE single-precision floating point numbers, explainwhat type of number they represent.
(i) 0b0111 1111 1000 1111 0000 1111 0000 0000
(ii) 0b0000 0000 0000 0000 0000 0000 0000 0000
(iii) 0b0100 0010 0100 0000 0000 0000 0000 0000
(iv) 0b1000 0000 0100 0000 0000 0000 0000 0000
4. How is branch address modification achieved using the Bit-ORing technique in a micro-programmed control unit?
5. Suppose a DRAM has a RAS-CAS delay of 45 ns, has a CAS-data delay of 35 ns,and requires a pre-charge time of 20 ns. If the DRAM does not support page mode and returns 4 bits of data from each memory reference, what is its latency for readoperations, throughput and bandwidth?6. Consider a three-level cache with access times of 5 ns, 20 ns, and 80 ns respectively. If the hit rates are 95%, 85% and 75% respectively in the three caches, what is the average access time?
7. Vector processor is essentially processor. True/False. Give reasons for your choice.
8. A program loop ends with a conditional to the beginning of the loop. How wouldyou implement this loop on a pipelined computer that uses delayed branchingwith one delay slot? Under what conditions would you be able to put a useful instruction in the delay slot?
9. How does a system with n-modular redundancy work? How fault tolerant is it?
10. List 3 unique features in the SPARC architecture.
PART – B(5 x 16 = 80 Marks)
11a. Consider designing a pipeline for a DMA controller. What would be the various stages of the pipelines? Can you obtain any advantage? Explain (6 Marks)
b. Design the memory system (512 MB) for a processor with 3 memory ports for read and write (i.e it can simultaneously read and write 3 operands), whose access time is 3 times the processor clock period. Comment on the suitability of your memory system for efficient access with vector processors, or add features to your design to make it suitable. Clearly indicate the option that you have considered, and justify every choice that you have made. (10 Marks)
12a. i) A new microprocessor is designed with a conventional architecture employing single-address instruction and 8-bit words. Due to physical size constraints, only eight distinct opcodes are allowed. The use of modifiers or the address field to extend the opcodes if forbidden. (a) Which eight instructions would you implement? Specify the operations performed by each instruction as well as the location of its operands. (10 Marks)
ii) Demonstrate that your instruction set is functionally complete in some reasonablesense; or describe an operation that cannot be programmed in your instruction set.(6 Marks)
(OR)
12b. i) Give the structure of 0-operand, 1 operand, 2-operand, and 3-operand instructionformats. What are the typical instructions for which each of them is suited? How are these handled in different processor architectures? (8 Marks)
ii) Consider executing the function C ? Sum of Ai * Bi for all I = 1 to n.Write the code to implement this on a single-accumulator processor. Does this look like an efficient way of implementing this function? Which addressing modes would you use – if you had a choice. Which architecture would be better suited for this kind of operation? (8 Marks)
13a. Design a microprogrammed control unit for a multiplier (using shift-add operations). Give the complete design. (16 Marks)
(OR)
13b. i) Explain the design of a pipelined floating point adder/subtractor. (10 Marks)
ii) A BGT (Branch if > 0) machine instruction has the expression Z+(N+V) = 0 as itsits branch condition, where Z, N and V are the zero, negative and overflow condition flags respectively. Write a micro-routine that can implement this instruction. Show the circuitry needed to test the condition codes. (6 Marks)
14a. i) A byte-addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consists of 1 32-bit word. When a given program is executed, the processor reads data from the following sequence of hex addresses –200, 204, 208, 20C, 2F0, 200, 204, 218, 21C, 24C, 2F4. The pattern is repeated 4 times.Assuming that the cache is initially empty, show the contents of the cache at the end of each pass, and compute the hit rate for (A). Direct mapped cache (B). 4-way set associative cache. (10 Marks)
ii) Compare program controlled I/O with interrupt based processing of I/O. In which cases are the two schemes more suitable? (6 Marks)
(OR)
14b. i) A 1024 x 1024 array of 32-bit numbers is to be normalized as follows. For each column, the largest element is found, and all elements of that column are divided by that maximum value. Assume that each page in the virtual memory consists of 4K bytes, and that 1M bytes of main memory are allocated for storing data during this computation. Assume it takes 40 ms to load page from the disk into tha main memory when a page fault occurs. How many page faults would occur if the elements were stored in row order? How many would occur if they were stored in column order? Estimate the total time needed to perform the normalization in both cases. (10 Marks)
ii) How is arbitration for the bus handled during DMA? (6 Marks)
15a. i) Discuss the various techniques used to handled control hazards in a pipelined processor. (10 Marks)
ii) Discuss the various fault-tolerance techniques used. (6 Marks)
(OR)
15b. i) Consider the following sequence of instructions.
Add #20, R0, R1
Mul #3, R2, R3
AND #$3A, R2, R4
Add R0, R2, R5
In all instructions the destination is given last. Initially registers R0 and R2 contain 2000, and 50 respectively. These instruction are executed on a 4-stage pipeline. Show the sequence of operations using a pipe-line timing diagram. Explain each step. Give the contents of the interstage buffers B1, B2, and B3 during clock cycles 2 to 5. (10 Marks)
ii) Differentiate between RISC and CISC processors. (6 Marks)

B.E./B.Tech. DEGREE EXAMINATION,--III Semester

IF 245 — COMPUTER ARCHITECTURE

Time : 3 hours Maximum : 100 marks

Answer ALL questions.

(10 X 2 = 20 marks)

1. Define the terms software compatibility and hardware compatibility, What role have they played in the evolution of computers?

2. Discuss the stored program concept,. What are its advantages and disadvantages?

3. What are the requirements to be satisfied by an instruction set?

4. Discuss the relative merits and demerits of a hardwired control unit ,and a microprogrammed control unit.

5. What is a TLB? What is its use?

6. A two level memory (M1, M2) has the access times tA1 = 10–8 sec., and
tA2 = 10–3 sec. What must the hit ratio H be in order for the access efficiency to be atleast 65% of its maximum possible value?

7. Consider an unpipelined machine that has 10 ns. ,clock cycles and uses four cycles for ALU operations and branches and five cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and set up, pipelining the machine adds 1 ns of overhead to the clock. Ignoring any latency impact much speed up in the instruction execution rate will we gain from a pipeline.

8.Discuss the Flyan’s classification of computers.

9. Distinguish between RISC and CISC machines.

10. What is meant by reliability?, How is it defined for a series and parallel system?

PART B — (16 X5= 80 marks)

11].(i) What are the different hazards that might arise in a pipeline? ,How are they overcome? [8]

(ii) Give the organization of a floating point adder/subtractor unit and explain its operation. [8]

12].(a) (i) What is a stack processor? ,Show the stack states during the execution of . [6]

(ii) Discuss the different addressing modes used typically in RISC processors. [5]

(iii) What are the different types of instructions found in processors? ,Discuss. [5]

Or

12].(b) (i) How should an instruction format be designed?, Discuss the different types of instruction formats, bringing out their relative advantages and disadvantages. (6]

(ii) How do you determine the instruction execution speed of a processor?
Identify and briefly describe three distinct ways in which parallelism can be introduced into the micro architecture of a computer in order to increase its overall instruction execution speed. (10]

13].(a) (i) Give the organization of a two’s complement multiplier and discuss its operation. [8]

(ii) Discuss the organization of a microprogrammed control unit. ,How are branches implemented here? [8]

Or

13].(b) (i) Show how a 64 bit adder can be constructed using 4–bit adder modules and 4 bit carry look a head generator modules. What is the delay in generating C64 and S63 here? (8]

(ii) Discuss any one binary division algorithm and simulate the same for . [8]

14]. (a) (i) How is parallelism achieved in uniprocessor machines? Discuss. [6]

(ii) Discuss about an interrupt driven transfer and a DMA transfer clearly bringing out the advantages and disadvantages of each technique. (10)

Or

14].(b) (i) What are associative memories? ,How are they constructed and used? [8)

(ii) Consider the following page address trace generated by a two level cache main memory scheme that uses demand paging and has a cache capacity of four pages :
1 6 4 5 1 4 3 2 1 2 1 4 6 7 4.
Assuming the cache initially has pages 1, 2, 3 and 4, show the cache trace if LRU policy is used for replacement. Contrast this with FIFO replacement. (8)

15] (a) Discuss the architectural features of the SPARC processor.

Or

15](b) (i) Discuss the design principles used in typical RISC processors. [10)

(ii) What are the different ways in which redundancy can be made use of provide fault tolerance? [6)

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(PART A-10*2=20 marks)
1.What is load store architecture?
2.Explain the absolute and auto increment addressing modes with an example instruction?
3.Discuss the IEEE format used for representing single-precision floating point numbers.
4.Discuss the principle of operation of a carry saver adder.
5.What are the advantages and disadvantages of hardwired and micro-programmed control?
6.What is the ideal speedup expected in a pipelined architecture with ‘n’ stages? Justify your answer.
7.Distinguish between the write-through and write-back policies out their merits and demerits.
8.What is an interleaved memory system? Discuss.
9.Distinguish between memory and mapped I/O and I/O mapped I/O.
10.Consider a computer in which several devices are to be serviced interrupts. How do you handle this if the processor has only one request line?

(PART B-5*16=80 marks)
11.(i).Consider the following instruction
Add (R0)+R1,R2
Where the first two are source operands and the third is the destination operand. Show the control sequence to execute this instruction for a single bus organization assuming the instruction itself is only a one word instruction [Marks-8]
(ii).What are the features to be considered while designing the instruction formats of a
processor? Discuss in detail. [Marks-8]

12.a).(i).Discuss the principle of operation of carry look ahead adder. [Marks-4]
(ii).Design a 64-bit adder that uses four 16-bit carry-look ahead adders along with additional logic to generate c16,c32,c48 and c64 from c0 and the G1” and P1” variable. Also calculate the delay for generating s63 and c64. [Marks-12]
(Or)
12.b).(i).Discuss the operation of floating point adder/subtractor unit. [Marks-12]
(ii).Simulate the addition operations on the operands:
A=0 10001 011011
B=1 01111 101010
With a five-bit signed excess-15 exponent and six-bit normalized fractionalized
Mantissa. [Marks-4]

13.a).Give the organization of a typical hardwired control unit and explain the functions performed by the various blocks. Discuss the data flow for a simple instruction. [Marks-16]

(Or)

13.b).Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome/minimize these hazards. [Marks-16]

14.a).(i).Discuss the various mapping techniques used in cache memories. [Marks-12]
(ii).A computer system has a main memory consisting of 1M words. It also has 8K word cache organized in the block-set-associative manner, with 4 blocks per set and 64 words per block. [Marks-4]
(Or)

14.b).(i).Explain the concept of virtual memory with any one virtual memory management techniques. [Marks-12]
(ii).Give the basic cell of an associative memory and explain its operation. [Marks-4]

15.a).(i).What are the functions performed by a typical I/O interface? [Marks-4]
(ii).Explain the interrupt driven mode of data transfer and the DMA driven data transfer elaborating on how they are accomplished and their relative merits and demerits. [Marks-12]

(Or)
15.b).Write short notes on the following
(i).Laser printers [Marks-8]
(ii).Any two input devices [Marks-8]